FIG. 1 schematically illustrates a conventional MOSFET device 10, in particular an N-MOS device. The device comprises a P-well 12 which is formed in an N-type silicon substrate (not shown). The source and drain regions 14 and 16 are N.sup.+ type and are formed at the surface of the P-well 12. A gate structure is formed over the channel 18 between the source and drain regions. More specifically, gate 20 is formed from a conducting material such as polysilicon. The gate 20 is separated from the surface of the P-well by the gate oxide (SiO.sub.2) 22. Oxide spacers 24 and 26 are located on either side of the gate 20. The lightly doped regions 34 and 36 are provided to reduce the device hot carrier effects. The field oxide regions 38 are provided to separate adjacent MOS devices in an integrated circuit. A Metal-Poly-Dielectric (MPD) layer 42 is deposited over the surface of the device 10. Openings are formed in the MPD layer 42 so that metal contacts 44 and 46 can be made to the source and drain regions 14 and 16.
In the conventional device 10, the source and drain areas are large in order to allow for contact-to-gate and contact-to-FOX edge misalignment. The capacitance between the source and the P-well and the drain and the P-well is quite large. These capacitances are referred to or the "source/drain to substrate" capacitances. The large source/drain to substrate capacitances can degrade circuit performance seriously.
To overcome this problem, a self-aligned contact process has been developed. A MOSFET (an N-MOS device) which has been formed using the self-aligned contact process is illustrated in FIG. 2.
The N-MOS device 10' of FIG. 2 differs from the device 10 of FIG. 1 as follows. The gate 20 is enclosed by a dielectric 21 which may be oxide (SiO.sub.2) or nitride (Si.sub.3 N.sub.4). Moreover, the metal contacts 44 and 46 do not directly contact the source and drain regions 14 and 16 (as shown in FIG. 1). Instead, In FIG. 2, the interconnects 54 and 56 directly contact the source and drain 14 and 16. The interconnects 54 and 56 may be formed in part directly over the FOX regions 38 or over the gate enclosing dielectric 21. The metal contacts 44 and 46 then contact the interconnects 54 and 56. For this reason, the source and drain regions 14 and 16 may be smaller in the device 10' of FIG. 2 than in the device 10 of FIG. 1.
However, the device 10' of FIG. 2 still has a certain deficiency. The area of the source and drain 14 and 16 (or more particularly, the area at which the interconnects 54 and 56 contact the source and drain 14 and 16) must still be large enough to account for the worst case misalignment between the gate and field oxide (FOX) region that is still acceptable for proper source and drain connection. Thus, even in the device 10' of FIG. 2, the source and drain regions 14 and 16 still have a substantial size.
It is an object of the present invention to provide a self-aligned contact process for making a MOS device which overcomes the deficiencies of the prior art MOS devices. More particularly, it is an object of the invention to provide a self-aligned contact process for making a MOS device in which the source and drain regions are smaller than devices made using a conventional self-aligned process.